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* Use a raw_stream to implement the mangler.Rafael Espindola2014-01-29
| | | | | | | | | This is a bit more convenient for some callers, but more importantly, it is easier to implement correctly. Doing this removes the patching of already printed data that was used for fastcall, fixing a crash with private fastcall symbols. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200367 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64 NEON] Lower SELECT_CC with vector operand.Kevin Qin2014-01-29
| | | | | | | | When the scalar compare is between floating point and operands are vector, we custom lower SELECT_CC to use NEON SIMD compare for generating less instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200365 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Remove superfluous inline asm mode switch testDavid Woodhouse2014-01-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200361 91177308-0d34-0410-b5e6-96231b3b80d8
* Tests for mode switchingDavid Woodhouse2014-01-28
| | | | | | | 1. test that inlineasm works 2. test that relaxable instructions are re-encoded in the correct mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200351 91177308-0d34-0410-b5e6-96231b3b80d8
* Disable the COFF tests on non-X86 archsTimur Iskhodzhanov2014-01-28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200341 91177308-0d34-0410-b5e6-96231b3b80d8
* Add line table debug info to COFF files when using a win32 triple.Timur Iskhodzhanov2014-01-28
| | | | | | Reviewed at http://llvm-reviews.chandlerc.com/D2232 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200340 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix ELF header flags.Matheus Almeida2014-01-28
| | | | | | | | | As opposed to GCC/GAS the default ABI for Mips64 is n64. Compatibility bit should be set if o32 ABI is used when targeting Mips64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200332 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Fix emitting aggregate parametersGautam Chakrabarti2014-01-28
| | | | | | | | | | The code was missing the case for aggregate parameters and hence was emitting them as .b0 type. Also fixed a couple of comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200325 91177308-0d34-0410-b5e6-96231b3b80d8
* [X86] Add extra rules for combining vselect dag nodes into movsd.Andrea Di Biagio2014-01-28
| | | | | | | | | | | | | | | | | | | | | | This improves the fix committed at revision 199683 adding the following new target specific combine rules: 1) fold (v4i32: vselect <0,0,-1,-1>, A, B) -> (v4i32 (bitcast (movsd (v2i64 (bitcast A)), (v2i64 (bitcast B))) )) 2) fold (v4f32: vselect <0,0,-1,-1>, A, B) -> (v4f32 (bitcast (movsd (v2f64 (bitcast A)), (v2f64 (bitcast B))) )) 3) fold (v4i32: vselect <-1,-1,0,0>, A, B) -> (v4i32 (bitcast (movsd (v2i64 (bitcast B)), (v2i64 (bitcast A))) )) 4) fold (v4f32: vselect <-1,-1,0,0>, A, B) -> (v4f32 (bitcast (movsd (v2i64 (bitcast B)), (v2i64 (bitcast A))) )) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200324 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix pr14893.Rafael Espindola2014-01-28
| | | | | | | | | | | When simplifycfg moves an instruction, it must drop metadata it doesn't know is still valid with the preconditions changes. In particular, it must drop the range and tbaa metadata. The patch implements this with an utility function to drop all metadata not in a white list. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200322 91177308-0d34-0410-b5e6-96231b3b80d8
* [DAGCombiner] Avoid introducing an illegal build_vector when folding a ↵Andrea Di Biagio2014-01-28
| | | | | | | | | | | | | | | | | | sign_extend. Make sure that we don't introduce illegal build_vector dag nodes when trying to fold a sign_extend of a build_vector. This fixes a regression introduced by r200234. Added test CodeGen/X86/fold-vector-sext-crash.ll to verify that llc no longer crashes with an assertion failure due to an illegal build_vector of type MVT::v4i64. Thanks to Ilia Filippov for spotting this regression and for providing a reproducible test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200313 91177308-0d34-0410-b5e6-96231b3b80d8
* [vectorizer] Completely disable the block frequency guidance of the loopChandler Carruth2014-01-28
| | | | | | | | | | | | | | | vectorizer, placing it behind an off-by-default flag. It turns out that block frequency isn't what we want at all, here or elsewhere. This has been I think a nagging feeling for several of us working with it, but Arnold has given some really nice simple examples where the results are so comprehensively wrong that they aren't useful. I'm planning to email the dev list with a summary of why its not really useful and a couple of ideas about how to better structure these types of heuristics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200294 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle spilling the PPC GPRC_NOR0 register classHal Finkel2014-01-28
| | | | | | | GPRC_NOR0 is not a subclass of GPRC (because it also contains the ZERO pseudo register). As a result, we also need to check for it in the spilling code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200288 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add pattern for truncating i32 to i1Michel Danzer2014-01-28
| | | | | | | | Fixes half a dozen piglit tests with radeonsi. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200283 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the DWARF EH encodings for Sparc PIC code.Jakob Stoklund Olesen2014-01-28
| | | | | | | Also emit the stubs that were generated for references to typeinfo symbols. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200282 91177308-0d34-0410-b5e6-96231b3b80d8
* Update optimization passes to handle inalloca argumentsReid Kleckner2014-01-28
| | | | | | | | | | | | | | | Summary: I searched Transforms/ and Analysis/ for 'ByVal' and updated those call sites to check for inalloca if appropriate. I added tests for any change that would allow an optimization to fire on inalloca. Reviewers: nlewycky Differential Revision: http://llvm-reviews.chandlerc.com/D2449 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200281 91177308-0d34-0410-b5e6-96231b3b80d8
* LoopVectorize: Support conditional stores by scalarizingArnold Schwaighofer2014-01-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The vectorizer takes a loop like this and widens all instructions except for the store. The stores are scalarized/unrolled and hidden behind an "if" block. for (i = 0; i < 128; ++i) { if (a[i] < 10) a[i] += val; } for (i = 0; i < 128; i+=2) { v = a[i:i+1]; v0 = (extract v, 0) + 10; v1 = (extract v, 1) + 10; if (v0 < 10) a[i] = v0; if (v1 < 10) a[i] = v1; } The vectorizer relies on subsequent optimizations to sink instructions into the conditional block where they are anticipated. The flag "vectorize-num-stores-pred" controls whether and how many stores to handle this way. Vectorization of conditional stores is disabled per default for now. This patch also adds a change to the heuristic when the flag "enable-loadstore-runtime-unroll" is enabled (off by default). It unrolls small loops until load/store ports are saturated. This heuristic uses TTI's getMaxUnrollFactor as a measure for load/store ports. I also added a second flag -enable-cond-stores-vec. It will enable vectorization of conditional stores. But there is no cost model for vectorization of conditional stores in place yet so this will not do good at the moment. rdar://15892953 Results for x86-64 -O3 -mavx +/- -mllvm -enable-loadstore-runtime-unroll -vectorize-num-stores-pred=1 (before the BFI change): Performance Regressions: Benchmarks/Ptrdist/yacr2/yacr2 7.35% (maze3() is identical but 10% slower) Applications/siod/siod 2.18% Performance improvements: mesa -4.42% libquantum -4.15% With a patch that slightly changes the register heuristics (by subtracting the induction variable on both sides of the register pressure equation, as the induction variable is probably not really unrolled): Performance Regressions: Benchmarks/Ptrdist/yacr2/yacr2 7.73% Applications/siod/siod 1.97% Performance Improvements: libquantum -13.05% (we now also unroll quantum_toffoli) mesa -4.27% git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200270 91177308-0d34-0410-b5e6-96231b3b80d8
* PGO branch weight: keep halving the weights until they can fit intoManman Ren2014-01-27
| | | | | | | | | | | uint32. When folding branches to common destination, the updated branch weights can exceed uint32 by more than factor of 2. We should keep halving the weights until they can fit into uint32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200262 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM MC: Fix the initial DWARF CFI unwind info at the start of a functionMark Seaborn2014-01-27
| | | | | | | | | | | | | | | | | | | | This brings MC into line with GNU 'as' on ARM, and it brings the ARM target into line with most other LLVM targets, which declare the initial CFI state with addInitialFrameState(). Without this, functions generated with .cfi_startproc/endproc on ARM will tend to cause GDB to abort with: gdb/dwarf2-frame.c:1132: internal-error: Unknown CFA rule. I've also tested this by comparing the output of "readelf -w" on the object files produced by llvm-mc and gas when given the .s file added here. This change is part of addressing PR18636. Differential Revision: http://llvm-reviews.chandlerc.com/D2597 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200255 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix unsupported addressing mode assertion for pldDavid Peixotto2014-01-27
| | | | | | | | | | | | | | | | | | | | Summary: This commit gives an address mode to the PLD instruction. We were getting an assertion failure in the frame lowering code because we had code that was doing a pld of a stack allocated address. The frame lowering was checking the address mode and then asserting because pld had none defined. This commit fixes pld for arm mode. There was a previous fix for thumb mode in a separate commit. The commit for thumb mode added a test in a separate file because it would otherwise fail for arm. This commit moves the thumb test back into the prefetch.ll file and adds the corresponding arm test. Differential Revision: http://llvm-reviews.chandlerc.com/D2622 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200248 91177308-0d34-0410-b5e6-96231b3b80d8
* [DAGCombiner] Teach how to fold sext/aext/zext of constant build vectors.Andrea Di Biagio2014-01-27
| | | | | | | | | | | | | | | This patch teaches the DAGCombiner how to fold a sext/aext/zext dag node when the operand in input is a build vector of constants (or UNDEFs). The inability to fold a sext/zext of a constant build_vector was the root cause of some pcg bugs affecting vselect expansion on x86-64 with AVX support. Before this change, the DAGCombiner only knew how to fold a sext/zext/aext of a ConstantSDNode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200234 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: Add support for .cfi_startproc simpleDavid Majnemer2014-01-27
| | | | | | | | | | | | | | This commit allows LLVM MC to process .cfi_startproc directives when they are followed by an additional `simple' identifier. This signals to elide the emission of target specific CFI instructions that would normally occur initially. This fixes PR16587. Differential Revision: http://llvm-reviews.chandlerc.com/D2624 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200227 91177308-0d34-0410-b5e6-96231b3b80d8
* [vectorize] Initial version of respecting PGO in the vectorizer: treatChandler Carruth2014-01-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | cold loops as-if they were being optimized for size. Nothing fancy here. Simply test case included. The nice thing is that we can now incrementally build on top of this to drive other heuristics. All of the infrastructure work is done to get the profile information into this layer. The remaining work necessary to make this a fully general purpose loop unroller for very hot loops is to make it a fully general purpose loop unroller. Things I know of but am not going to have time to benchmark and fix in the immediate future: 1) Don't disable the entire pass when the target is lacking vector registers. This really doesn't make any sense any more. 2) Teach the unroller at least and the vectorizer potentially to handle non-if-converted loops. This is trivial for the unroller but hard for the vectorizer. 3) Compute the relative hotness of the loop and thread that down to the various places that make cost tradeoffs (very likely only the unroller makes sense here, and then only when dealing with loops that are small enough for unrolling to not completely blow out the LSD). I'm still dubious how useful hotness information will be. So far, my experiments show that if we can get the correct logic for determining when unrolling actually helps performance, the code size impact is completely unimportant and we can unroll in all cases. But at least we'll no longer burn code size on cold code. One somewhat unrelated idea that I've had forever but not had time to implement: mark all functions which are only reachable via the global constructors rigging in the module as optsize. This would also decrease the impact of any more aggressive heuristics here on code size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200219 91177308-0d34-0410-b5e6-96231b3b80d8
* ConstantHoisting: We can't insert instructions directly in front of a PHI node.Benjamin Kramer2014-01-27
| | | | | | Insert before the terminating instruction of the dominating block instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200218 91177308-0d34-0410-b5e6-96231b3b80d8
* [vectorizer] Add an override for the target instruction cost and use itChandler Carruth2014-01-27
| | | | | | | to stabilize a test that really is trying to test generic behavior and not a specific target's behavior. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200215 91177308-0d34-0410-b5e6-96231b3b80d8
* [vectorizer] Teach the loop vectorizer's unroller to only unroll byChandler Carruth2014-01-27
| | | | | | | | | | | | | | | | | | | | | | | | | powers of two. This is essentially always the correct thing given the impact on alignment, scaling factors that can be used in addressing modes, etc. Also, fix the management of the unroll vs. small loop cost to more accurately model things with this world. Enhance a test case to actually exercise more of the unroll machinery if using synthetic constants rather than a specific target model. Before this change, with the added flags this test will unroll 3 times instead of either 2 or 4 (the two sensible answers). While I don't expect this to make a huge difference, if there are lots of loops sitting right on the edge of hitting the 'small unroll' factor, they might change behavior. However, I've benchmarked moving the small loop cost up and down in many various ways and by a huge factor (2x) without seeing more than 0.2% code size growth. Small adjustments such as the series that led up here have led to about 1% improvement on some benchmarks, but it is very close to the noise floor so I mostly checked that nothing regressed. Let me know if you see bad behavior on other targets but I don't expect this to be a sufficiently dramatic change to trigger anything. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200213 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix crasher introduced in r200203 and caught by a libc++ buildbot. Don't ↵Nick Lewycky2014-01-27
| | | | | | assume that getMulExpr returns a SCEVMulExpr, it may have simplified it to something else! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200210 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach SCEV to handle more cases of 'and X, CST', specifically where CST is ↵Nick Lewycky2014-01-27
| | | | | | | | | | | any number of contiguous 1 bits in a row, with any number of leading and trailing 0 bits. Unfortunately, this in turn led to some lower quality SCEVs due to some different paths through expression simplification, so add getUDivExactExpr and use it. This fixes all instances of the problems that I found, but we can make that function smarter as necessary. Merge test "xor-and.ll" into "and-xor.ll" since I needed to update it anyways. Test 'nsw-offset.ll' analyzes a little deeper, %n now gets a scev in terms of %no instead of a SCEVUnknown. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200203 91177308-0d34-0410-b5e6-96231b3b80d8
* Additional fix for 200201: due to dependence on bitwidth test was moved to ↵Stepan Dyatkovskiy2014-01-27
| | | | | | X86 directory. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200202 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix for PR18102.Stepan Dyatkovskiy2014-01-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Issue outcomes from DAGCombiner::MergeConsequtiveStores, more precisely from mem-ops sequence sorting. Consider, how MergeConsequtiveStores works for next example: store i8 1, a[0] store i8 2, a[1] store i8 3, a[1] ; a[1] again. return ; DAG starts here 1. Method will collect all the 3 stores. 2. It sorts them by distance from the base pointer (farthest with highest index). 3. It takes first consecutive non-overlapping stores and (if possible) replaces them with a single store instruction. The point is, we can't determine here which 'store' instruction would be the second after sorting ('store 2' or 'store 3'). It happens that 'store 3' would be the second, and 'store 2' would be the third. So after merging we have the next result: store i16 (1 | 3 << 8), base ; is a[0] but bit-casted to i16 store i8 2, a[1] So actually we swapped 'store 3' and 'store 2' and got wrong contents in a[1]. Fix: In sort routine just also take into account mem-op sequence number. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200201 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add intrinsic for BUFFER_LOAD_DWORD* instructionsMichel Danzer2014-01-27
| | | | | | Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200196 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add intrinsic for S_SENDMSG instructionMichel Danzer2014-01-27
| | | | | | Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200195 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename IMAGE_DLL_CHARACTERISTICS_HIGH_ENTROPY_VA.Rui Ueyama2014-01-27
| | | | | | | editbin.exe and link.exe both accepts /highentropyva option to set this bit, so doing s/VIRTUAL_ADDRESS/VA/ should make sense. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200191 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64 NEON] Try to generate CONCAT_VECTOR when lowering BUILD_VECTOR or ↵Kevin Qin2014-01-27
| | | | | | | | SHUFFLE_VECTOR. Replace r199791. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200180 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r199791.Kevin Qin2014-01-27
| | | | | | It's old version which has some bugs. I'll commit lattest patch soon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200179 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: fix test locations/nameSaleem Abdulrasool2014-01-26
| | | | | | | Placed the MC variant diagnostics in the wrong directory accidentally. Move them into their respective architecture specific directories. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200161 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: improve diagnostics for .word directiveSaleem Abdulrasool2014-01-26
| | | | | | | | | If a complex expression was passed to the .word directive and the first part of the directive failed to parse, a secondary diagnostic would be produced that would clutter the error diagnostics. Improve the diagnostics by consuming the remainder of the statement. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200160 91177308-0d34-0410-b5e6-96231b3b80d8
* AsmParser: improve diagnostics for invalid variantsSaleem Abdulrasool2014-01-26
| | | | | | | | | An emitted diagnostic for an invalid relocation variant would place the caret on the token following the relocation variant indicator or at the end of the line if there was no following token. This change corrects the placement of the caret to point to the token. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200159 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up the Legal/Expand logic for SPARC popc.Jakob Stoklund Olesen2014-01-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200141 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement the missing bits corresponding to .mips_hack_elf_flags.Rafael Espindola2014-01-26
| | | | | | | | | | | | These were: * noreorder handling on the target object streamer and asm parser. * setting the initial flag bits based on the enabled features. * setting the elf header flag for micromips It is *really* depressing I am the one doing this instead of someone at mips actually taking the time to understand the infrastructure. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200138 91177308-0d34-0410-b5e6-96231b3b80d8
* Only generate the popc instruction for SPARC CPUs that implement it.Jakob Stoklund Olesen2014-01-26
| | | | | | | The popc instruction is defined in the SPARCv9 instruction set architecture, but it was emulated on CPUs older than Niagara 2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200131 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix swapped CASA operands.Jakob Stoklund Olesen2014-01-26
| | | | | | Found by SingleSource/UnitTests/AtomicOps.c git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200130 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Add support for parsing DW_CFA_GNU_window_save. Venkatraman Govindaraju2014-01-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200127 91177308-0d34-0410-b5e6-96231b3b80d8
* COFF: Add a missing enum value for high entropy ASLR.Rui Ueyama2014-01-26
| | | | | | | | | That bit is not documented in the PE/COFF spec published by Microsoft, so we don't know the official name of it. I named this bit IMAGE_DLL_CHARACTERISTICS_HIGH_ENTROPY_VIRTUAL_ADDRESS because the bit is reported as "high entropy virtual address" by dumpbin.exe, git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200121 91177308-0d34-0410-b5e6-96231b3b80d8
* Improve pattern match from v1i8 to v1i32 for AArch64 Neon.Jiangning Liu2014-01-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200119 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm-readobj: add support for PE32+ (Windows 64 bit executable).Rui Ueyama2014-01-26
| | | | | | | | | | | | PE32+ supports 64 bit address space, but the file format remains 32 bit. So its file format is pretty similar to PE32 (32 bit executable). The differences compared to PE32 are (1) the lack of "BaseOfData" field and (2) some of its data members are 64 bit. In this patch, I added a new member function to get a PE32+ Header object to COFFObjectFile class and made llvm-readobj to use it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200117 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove -print-hack-directives from a test where we already do the right thing.Rafael Espindola2014-01-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200116 91177308-0d34-0410-b5e6-96231b3b80d8
* Move tests that just use llc from test/MC/Mips to test/MC/Codegen.Rafael Espindola2014-01-26
| | | | | | This is an expanded version of r200064. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200115 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement pattern match from v1xx to v1xx for AArch64 Neon.Jiangning Liu2014-01-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200113 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Add support for sparc relocation types in ELF object file.Venkatraman Govindaraju2014-01-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200112 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-14 22:29:05 +0000