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path: root/lib/Target/X86/PeepholeOptimizer.cpp
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* Renamed files to have the `X86' prefix for uniqueness purposes.Misha Brukman2004-07-26
| | | | | | | All CVS history was renamed, the *,v were copied over. No worries. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15238 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert to the new TargetMachine interface.Chris Lattner2004-06-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13952 91177308-0d34-0410-b5e6-96231b3b80d8
* Add more ADC and SBB variantsAlkis Evlogimenos2004-04-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12607 91177308-0d34-0410-b5e6-96231b3b80d8
* A big X86 instruction rename. The instructions are renamed to makeAlkis Evlogimenos2004-02-29
| | | | | | | | | | | | | | | | | their names more decriptive. A name consists of the base name, a default operand size followed by a character per operand with an optional special size. For example: ADD8rr -> add, 8-bit register, 8-bit register IMUL16rmi -> imul, 16-bit register, 16-bit memory, 16-bit immediate IMUL16rmi8 -> imul, 16-bit register, 16-bit memory, 8-bit immediate MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11995 91177308-0d34-0410-b5e6-96231b3b80d8
* Uncomment instructions that take both an immediate and a memoryAlkis Evlogimenos2004-02-28
| | | | | | | operand but their sizes differ. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11969 91177308-0d34-0410-b5e6-96231b3b80d8
* Do not generate instructions with mismatched memory/immediate sizedAlkis Evlogimenos2004-02-28
| | | | | | | operands. The X86 backend doesn't handle them properly right now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11944 91177308-0d34-0410-b5e6-96231b3b80d8
* Move MOTy::UseType enum into MachineOperand. This eliminates theAlkis Evlogimenos2004-02-22
| | | | | | | | | | switch statements in the constructors and simplifies the implementation of the getUseType() member function. You will have to specify defs using MachineOperand::Def instead of MOTy::Def though (similarly for Use and UseAndDef). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11715 91177308-0d34-0410-b5e6-96231b3b80d8
* The two address pass cannot handle two addr instructions where one incomingChris Lattner2004-02-22
| | | | | | | | | value is a physreg and one is a virtreg. For this reason, disable copy folding entirely for physregs. Also, use the new isMoveInstr target hook which gives us folding of FP moves as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11700 91177308-0d34-0410-b5e6-96231b3b80d8
* Add OR and XOR memory operand support.Alkis Evlogimenos2004-02-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11549 91177308-0d34-0410-b5e6-96231b3b80d8
* Peephole optimize SUBmi{16,32} into SUBmi{16,32}b when immediate is 8Alkis Evlogimenos2004-02-17
| | | | | | | bits wide. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11548 91177308-0d34-0410-b5e6-96231b3b80d8
* ADDmi{16,32} should be in the next case statement.Alkis Evlogimenos2004-02-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11547 91177308-0d34-0410-b5e6-96231b3b80d8
* Disable this peephole for now. We can't keep track of the fact that the ↵Chris Lattner2004-02-17
| | | | | | | | | immediate is 8 bits, but the memory reference is full sized. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11536 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the mneumonics for the mov instructions to have the source and destinationChris Lattner2004-02-17
| | | | | | | order in the correct sense!! Arg! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11530 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the last crimes against nature that used the 'ir' ordering to use theChris Lattner2004-02-17
| | | | | | | | 'ri' ordering instead... no it's not possible to store a register into an immediate! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11529 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename MOVi[mr] instructions to MOV[rm]iChris Lattner2004-02-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11527 91177308-0d34-0410-b5e6-96231b3b80d8
* Whoops, got my cases swapped.Chris Lattner2004-02-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11526 91177308-0d34-0410-b5e6-96231b3b80d8
* Add mem forms of AND instructionsChris Lattner2004-02-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11521 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename the IMULri* instructions to IMULrri, as they are actually three addressChris Lattner2004-02-17
| | | | | | | instructions. Add forms of these instructions that read from memory git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11518 91177308-0d34-0410-b5e6-96231b3b80d8
* Add peephole optimizations for ADD [MEM], IMM8 instructions.Alkis Evlogimenos2004-02-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11511 91177308-0d34-0410-b5e6-96231b3b80d8
* Make dense maps keyed on physical registers smallerusingAlkis Evlogimenos2004-02-15
| | | | | | | | | | | MRegisterInfo::getNumRegs() instead of MRegisterInfo::FirstVirtualRegister. Also use MRegisterInfo::is{Physical,Virtual}Register where appropriate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11477 91177308-0d34-0410-b5e6-96231b3b80d8
* Use newly added next() and prior() utility functions.Alkis Evlogimenos2004-02-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11430 91177308-0d34-0410-b5e6-96231b3b80d8
* Change MachineBasicBlock's vector of MachineInstr pointers into anAlkis Evlogimenos2004-02-12
| | | | | | | | | | ilist of MachineInstr objects. This allows constant time removal and insertion of MachineInstr instances from anywhere in each MachineBasicBlock. It also allows for constant time splicing of MachineInstrs into or out of MachineBasicBlocks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11340 91177308-0d34-0410-b5e6-96231b3b80d8
* Add #includeChris Lattner2004-02-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11285 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove uses of MachineOperand::isVirtualRegisterChris Lattner2004-02-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11281 91177308-0d34-0410-b5e6-96231b3b80d8
* Modify the two address instruction pass to remove the duplicateAlkis Evlogimenos2004-02-04
| | | | | | | operand of the instruction and thus simplify the register allocation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11124 91177308-0d34-0410-b5e6-96231b3b80d8
* Change interface of MachineOperand as follows:Alkis Evlogimenos2003-12-14
| | | | | | | | | | | | | | | | a) remove opIsUse(), opIsDefOnly(), opIsDefAndUse() b) add isUse(), isDef() c) rename opHiBits32() to isHiBits32(), opLoBits32() to isLoBits32(), opHiBits64() to isHiBits64(), opLoBits64() to isLoBits64(). This results to much more readable code, for example compare "op.opIsDef() || op.opIsDefAndUse()" to "op.isDef()" a pattern used very often in the code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10461 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a new SSA-based peephole optimizer which includes copy propagation andChris Lattner2003-12-01
| | | | | | | | | folding of instructions into addressing modes. This creates lots of dead instructions, which are currently not deleted. It also creates a lot of instructions that the X86 backend currently cannot handle. :( git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10275 91177308-0d34-0410-b5e6-96231b3b80d8
* Finegrainify namespacificationChris Lattner2003-11-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10270 91177308-0d34-0410-b5e6-96231b3b80d8
* Put all LLVM code into the llvm namespace, as per bug 109.Brian Gaeke2003-11-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9903 91177308-0d34-0410-b5e6-96231b3b80d8
* Added LLVM project notice to the top of every C++ source file.John Criswell2003-10-20
| | | | | | | Header files will be on the way. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9298 91177308-0d34-0410-b5e6-96231b3b80d8
* Emit x86 instructions for: A = B op C, where A and B are 16-bit registers,Chris Lattner2003-10-20
| | | | | | | | | | | | | | | | | | | | | | | C is a constant which can be sign-extended from 8 bits without value loss, and op is one of: add, sub, imul, and, or, xor. This allows the JIT to emit the one byte version of the constant instead of the two or 4 byte version. Because these instructions are very common, this can save a LOT of code space. For example, I sampled two benchmarks, 176.gcc and 254.gap. BM Old New Reduction 176.gcc 2673621 2548962 4.89% 254.gap 498261 475104 4.87% Note that while the percentage is not spectacular, this did eliminate 124.6 _KILOBYTES_ of codespace from gcc. Not bad. Note that this doesn't effect the llc version at all, because the assembler already does this optimization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9284 91177308-0d34-0410-b5e6-96231b3b80d8
* Factory methods for FunctionPasses now return type FunctionPass *.Brian Gaeke2003-08-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7823 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix problem with invalidated iteratorChris Lattner2003-01-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5327 91177308-0d34-0410-b5e6-96231b3b80d8
* New filesChris Lattner2003-01-13
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5260 91177308-0d34-0410-b5e6-96231b3b80d8
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