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* Revert r206732 which is causing llc to crash on most of the build bots.Chandler Carruth2014-04-21
| | | | | | | | Original commit message: Implement builtins for safe division: safe.sdiv.iN, safe.udiv.iN, safe.srem.iN, safe.urem.iN (iN = i8, i61, i32, or i64). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206735 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement builtins for safe division: safe.sdiv.iN, safe.udiv.iN, safe.srem.iN,Michael Zolotukhin2014-04-21
| | | | | | | | safe.urem.iN (iN = i8, i16, i32, or i64). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206732 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM64] Ports the Cortex-A53 Machine Model description from AArch64.Chad Rosier2014-04-18
| | | | | | | | | | | | | Summary: This port includes the rudimentary latencies that were provided for the Cortex-A53 Machine Model in the AArch64 backend. It also changes the SchedAlias for COPY in the Cyclone model to an explicit WriteRes mapping to avoid conflicts in other subtargets. Differential Revision: http://reviews.llvm.org/D3427 Patch by Dave Estes <cestes@codeaurora.org>! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206652 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: add more NEON tests.Tim Northover2014-04-18
| | | | | | | Mostly no testing this time, since they were just wrangling target-specific intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206613 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: disable generation of .loh directives outside MachO.Tim Northover2014-04-18
| | | | | | Part of PR19455. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206611 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: don't emit .subsections_via_symbols on ELF.Tim Northover2014-04-18
| | | | | | Part of PR19455. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206610 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: add extra NEG pattern.Tim Northover2014-04-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206609 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: port more AArch64 tests to ARM64.Tim Northover2014-04-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206592 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: add non-scalar lowering for more FCVT operations.Tim Northover2014-04-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206591 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: improve spotting of EXT instructions from VECTOR_SHUFFLE.Tim Northover2014-04-18
| | | | | | | We couldn't cope if the first mask element was UNDEF before, which isn't ideal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206588 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: spot a greater variety of concat_vector operations.Tim Northover2014-04-18
| | | | | | | | | | Code mostly copied from AArch64, just tidied up a trifle and plumbed into the ARM64 way of doing things. This also enables the AArch64 tests which inspired the previous untested commits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206574 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: implement cunning optimisation from AArch64Tim Northover2014-04-18
| | | | | | | | A vector extract followed by a dup can become a single instruction even if the types don't match. AArch64 handled this in ISelLowering, but a few reasonably simple patterns can take care of it in TableGen, so that's where I've put it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206573 91177308-0d34-0410-b5e6-96231b3b80d8
* Make test/CodeGen/ARM64/vector-insertion.ll explicitly select neon syntaxLouis Gerbarg2014-04-17
| | | | | | | Change the command line vector-insertion.ll to explicitly set the neon syntax to apple so that buildbots that default to other syntaxes won't fail. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206502 91177308-0d34-0410-b5e6-96231b3b80d8
* Improve ARM64 vector creationLouis Gerbarg2014-04-17
| | | | | | | | | | | This patch improves the performance of vector creation in caseiswhere where several of the lanes in the vector are a constant floating point value. It also includes new patterns to fold together some of the instructions when the value is 0.0f. Test cases included. rdar://16349427 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206496 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: [su]xtw use W regs as inputs, not X regs.Jim Grosbach2014-04-17
| | | | | | | | | Update the SXT[BHW]/UXTW instruction aliases and the shifted reg addressing mode handling. PR19455 and rdar://16650642 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206495 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: switch to IR-based atomic operations.Tim Northover2014-04-17
| | | | | | | | Goodbye code! (Game: spot the bug fixed by the change). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206490 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: add acquire/release versions of the existing atomic intrinsics.Tim Northover2014-04-17
| | | | | | | These will be needed to support IR-level lowering of atomic operations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206489 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM64] Fix "Cannot select" for vector ctpopAdam Nemet2014-04-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The commit of r205855: Author: Arnold Schwaighofer <aschwaighofer@apple.com> Date: Wed Apr 9 14:20:47 2014 +0000 SLPVectorizer: Only vectorize intrinsics whose operands are widened equally The vectorizer only knows how to vectorize intrinics by widening all operands by the same factor. Patch by Tyler Nowicki! exposed a backend bug causing a regression (Cannot select ctpop). The commit msg is a bit confusing because the patch actually changes the behavior for the loop-vectorizer as well. As things got refactored into a helper ctpop got snuck in to the trivially-vectorizable helper which is now used by both vectorizers. In other words, we started seeing vector-ctpops in the backend. This change makes ctpop LegalizeAction::Expand for the types not supported by the byte-only CNT instruction. We may be able to custom-lower these later to a single CNT but this is to fix the compiler crash first. Fixes <rdar://problem/16578951> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206433 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: port some NEON tests to ARM64Tim Northover2014-04-16
| | | | | | | | | These ones used completely different sets of intrinsics, so the only way to do it is create a separate ARM64 copy and change them all. Other than that, CodeGen was straightforward, no deficiencies detected here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206392 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: specify triple so that Linux tests passTim Northover2014-04-16
| | | | | | | Now that Linux is trying to reparse all inline asm it chokes on the different comment character in this test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206382 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: use 32-bit moves for constants where possible.Tim Northover2014-04-16
| | | | | | | | | | | | If we know that a particular 64-bit constant has all high bits zero, then we can rely on the fact that 32-bit ARM64 instructions automatically zero out the high bits of an x-register. This gives the expansion logic less constraints to satisfy and so sometimes allows it to pick better sequences. Came up while porting test/CodeGen/AArch64/movw-consts.ll: this will allow a 32-bit MOVN to be used in @test8 soon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206379 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: explicitly ask for Apple NEON syntax so test passes on LinuxTim Northover2014-04-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206368 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: mark x7 as used when an i128 gets shunted onto the stack.Tim Northover2014-04-16
| | | | | | | | The second half of a split i128 was ending up in x7, which is not a good thing. This is another part of PR19432. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206366 91177308-0d34-0410-b5e6-96231b3b80d8
* DAGCombiner: don't optimise non-existant litpool loadTim Northover2014-04-16
| | | | | | | | | | | This particular DAG combine is designed to kick in when both ConstantFPs will end up being loaded via a litpool, however those nodes have a semi-legal status, dictated by isFPImmLegal so in some cases there wouldn't have been a litpool in the first place. Don't try to be clever in those circumstances. Picked up while merging some AArch64 tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206365 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM64] Set default CPU to generic instead of cyclone.Quentin Colombet2014-04-15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206313 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r191049/r191059 as it can produce wrong code (see PR17975).Robert Lougher2014-04-15
| | | | | | | It has already been reverted on the 3.4 branch in r196521. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206311 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: add constraints to various FastISel operationsTim Northover2014-04-15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206284 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix for codegen bug that could cause illegal cmn instruction generationLouis Gerbarg2014-04-14
| | | | | | | | | | | In rare cases the dead definition elimination pass code can cause illegal cmn instructions when it replaces dead registers on instructions that use unmaterialized frame indexes. This patch disables the dead definition optimization for instructions which include frame index operands. rdar://16438284 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206208 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a flag to disable the ARM64DeadRegisterDefinitionsPassLouis Gerbarg2014-04-14
| | | | | | | This patch adds a -arm64-dead-def-elimination flag so that it is possible to disable dead definition elimination. Includes test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206207 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: remove buggy REV16 pattern.Tim Northover2014-04-14
| | | | | | The 32-bit pattern is still valid: 0123 -> 3210 -> 1032. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206172 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the ability to use GEPs for address sinking in CGPHal Finkel2014-04-12
| | | | | | | | | | | | | | | | | | | | | | | | | | The current memory-instruction optimization logic in CGP, which sinks parts of the address computation that can be adsorbed by the addressing mode, does this by explicitly converting the relevant part of the address computation into IR-level integer operations (making use of ptrtoint and inttoptr). For most targets this is currently not a problem, but for targets wishing to make use of IR-level aliasing analysis during CodeGen, the use of ptrtoint/inttoptr is a problem for two reasons: 1. BasicAA becomes less powerful in the face of the ptrtoint/inttoptr 2. In cases where type-punning was used, and BasicAA was used to override TBAA, BasicAA may no longer do so. (this had forced us to disable all use of TBAA in CodeGen; something which we can now enable again) This (use of GEPs instead of ptrtoint/inttoptr) is not currently enabled by default (except for those targets that use AA during CodeGen), and so aside from some PowerPC subtargets and SystemZ, there should be no change in behavior. We may be able to switch completely away from the ptrtoint/inttoptr sinking on all targets, but further testing is required. I've doubled-up on a number of existing tests that are sensitive to the address sinking behavior (including some store-merging tests that are sensitive to the order of the resulting ADD operations at the SDAG level). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206092 91177308-0d34-0410-b5e6-96231b3b80d8
* Add ARM64 CLS patternsLouis Gerbarg2014-04-11
| | | | | | | | | This patch adds patterns to generate the cls instruction ARM64. Includes tests for 64 bit and 32 bit operands. rdar://15611957 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206079 91177308-0d34-0410-b5e6-96231b3b80d8
* [DAGCombiner] DAG combine does not know how to combine indexed loads withQuentin Colombet2014-04-09
| | | | | | | | | | | | sign/zero/any extensions. However a few places were not checking properly the property of the load and were turning an indexed load into a regular extended load. Therefore the indexed value was lost during the process and this was triggering an assertion. <rdar://problem/16389332> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205923 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix some doc and comment typosAlp Toker2014-04-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205899 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM64] Rename LR to the UAL-compliant 'X30'.Bradley Smith2014-04-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205885 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM64] Rename FP to the UAL-compliant 'X29'.Bradley Smith2014-04-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205884 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: scalarize v1i64 mul operationTim Northover2014-04-09
| | | | | | This is the second part of fixing PR19367. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205836 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: add pattern for <1 x i64> custom not node.Tim Northover2014-04-09
| | | | | | This should fix PR19367. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205835 91177308-0d34-0410-b5e6-96231b3b80d8
* [Constant Hoisting][ARM64] Enable constant hoisting for ARM64.Juergen Ributzka2014-04-08
| | | | | | | | This implements the target-hooks for ARM64 to enable constant hoisting. This fixes <rdar://problem/14774662> and <rdar://problem/16381500>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205791 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: fix fmsub patterns which assumed accum operand was firstTim Northover2014-04-08
| | | | | | | | | | Confusingly, the NEON fmla instructions put the accumulator first but the scalar versions put it at the end (like the fma lib function & LLVM's intrinsic). This should fix PR19345, assuming there's only one issue. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205758 91177308-0d34-0410-b5e6-96231b3b80d8
* DAGLegalize: add last-ditch type-legalization for VSELECT.Tim Northover2014-04-04
| | | | | | | | | | | | | When LLVM sees something like (v1iN (vselect v1i1, v1iN, v1iN)) it can decide that the result is OK (v1i64 is legal on AArch64, for example) but it still need scalarising because of that v1i1. There was no code to do this though. AArch64 and ARM64 have DAG combines to produce efficient code and prevent that occuring in *most* such situations, but there are edge cases that they miss. This adds a legalization to cope with that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205626 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: handle v1i1 types arising from setcc properly.Tim Northover2014-04-04
| | | | | | | | | | | | | | | | | | | | There were several overlapping problems here, and this solution is closely inspired by the one adopted in AArch64 in r201381. Firstly, scalarisation of v1i1 setcc operations simply fails if the input types are legal. This is fixed in LegalizeVectorTypes.cpp this time, and allows AArch64 code to be simplified slightly. Second, vselect with such a setcc feeding into it ends up in ScalarizeVectorOperand, where it's not handled. I experimented with an implementation, but found that whatever DAG came out was rather horrific. I think Hao's DAG combine approach is a good one for quality, though there are edge cases it won't catch (to be fixed separately). Should fix PR19335. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205625 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: use regalloc-friendly COPY_TO_REGCLASS for bitcastsTim Northover2014-04-04
| | | | | | | | | | | | | | | | | | The previous patterns directly inserted FMOV or INS instructions into the DAG for scalar_to_vector & bitconvert patterns. This is horribly inefficient and can generated lots more GPR <-> FPR register traffic than necessary. It's much better to emit instructions the register allocator understands so it can coalesce the copies when appropriate. It led to at least one ISelLowering hack to avoid the problems, which was incorrect for v1i64 (FPR64 has no dsub). It can now be removed entirely. This should also fix PR19331. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205616 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: add 128-bit MLA operations to the custom selection code.Tim Northover2014-04-04
| | | | | | | | | | | Without this change, the llvm_unreachable kicked in. The code pattern being spotted is rather non-canonical for 128-bit MLAs, but it can happen and there's no point in generating sub-optimal code for it just because it looks odd. Should fix PR19332. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205615 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM64] Teach the ARM64DeadRegisterDefinition pass to respect implicit-defs.Lang Hames2014-04-03
| | | | | | | | | | | | | | | When rematerializing through truncates, the coalescer may produce instructions with dead defs, but live implicit-defs of subregs: E.g. %X1<def,dead> = MOVi64imm 2, %W1<imp-def>; %X1:GPR64, %W1:GPR32 These instructions are live, and their definitions should not be rewritten. Fixes <rdar://problem/16492408> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205565 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: add regression test for r205519.Tim Northover2014-04-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205520 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: don't generate __sincos_stret calls unless on MachOTim Northover2014-04-03
| | | | | | This should fix PR19314. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205514 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: use GOT for weak symbols & PIC.Tim Northover2014-04-02
| | | | | | | | | | Weak symbols cannot use the small code model's usual ADRP sequences since the instruction simply may not be able to encode a value of 0. This redirects them to use the GOT, which hopefully linkers are able to cope with even in the static relocation model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205426 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: fix lowering of fp128 fptosi/fptouiTim Northover2014-04-02
| | | | | | | We were creating libcall nodes that returned an MVT::f128, when these particular operations actually return an int of some stripe. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205425 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: make sure first argument to INSERT_SUBVECTOR has right type.Tim Northover2014-04-02
| | | | | | | | Again, coalescing and other optimisations swiftly made the MachineInstrs consistent again, but when compiled at -O0 a bad INSERT_SUBREGISTER was produced. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205423 91177308-0d34-0410-b5e6-96231b3b80d8
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