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* ScalarEvolution: Analyze trip count of loops with a switch guarding the exit.Benjamin Kramer2014-02-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201159 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach the DAGCombiner how to fold concat_vector nodes when the input is twoRobert Lougher2014-02-11
| | | | | | | | | | | | | | | BUILD_VECTOR nodes, e.g.: (concat_vectors (BUILD_VECTOR a1, a2, a3, a4), (BUILD_VECTOR b1, b2, b3, b4)) -> (BUILD_VECTOR a1, a2, a3, a4, b1, b2, b3, b4) This fixes an issue with AVX, where a sequence was not recognized as a 256-bit vbroadcast due to the concat_vectors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201158 91177308-0d34-0410-b5e6-96231b3b80d8
* [LPM] Switch LICM to actively use LCSSA in addition to preserving it.Chandler Carruth2014-02-11
| | | | | | | | | | | | | | | | | | | | | | | Fixes PR18753 and PR18782. This is necessary for LICM to preserve LCSSA correctly and efficiently. There is still some active discussion about whether we should be using LCSSA, but we can't just immediately stop using it and we *need* LICM to preserve it while we are using it. We can restore the old SSAUpdater driven code if and when there is a serious effort to remove the reliance on LCSSA from all of the loop passes. However, this also serves as a great example of why LCSSA is very nice to have. This change significantly simplifies the process of sinking instructions for LICM, and makes it quite a bit less expensive. It wouldn't even be as complex as it is except that I had to start the process of removing the big recursive LCSSA formation hammer in order to switch even this much of the re-forming code to asserting that LCSSA was preserved. I'll fully remove that next just to tidy things up until the LCSSA debate settles one way or the other. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201148 91177308-0d34-0410-b5e6-96231b3b80d8
* XCore target: fix const section handlingRobert Lytton2014-02-11
| | | | | | | | | | | | Xcore target ABI requires const data that is externally visible to be handled differently if it has C-language linkage rather than C++ language linkage. Clang now emits ".cp.rodata" section information. All other externally visible constant data will be placed in the DP section. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201144 91177308-0d34-0410-b5e6-96231b3b80d8
* XCore target: Lower ATOMIC_LOAD & ATOMIC_STORERobert Lytton2014-02-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201143 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX: fixed a bug in LowerVECTOR_SHUFFLEElena Demikhovsky2014-02-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201140 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Optimized BUILD_VECTOR pattern; Elena Demikhovsky2014-02-11
| | | | | | | fixed encoding of VEXTRACTPS instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201134 91177308-0d34-0410-b5e6-96231b3b80d8
* [CodeGenPrepare] Test case for the promotions that bypass theQuentin Colombet2014-02-11
| | | | | | | | | | profitability check due to some other checks in the addressing mode matcher. I.e., test case for commit r201121. <rdar://problem/16020230> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201132 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Initialize M0 and emit S_WQM_B64 whenever DS instructions are usedTom Stellard2014-02-10
| | | | | | | | | | | DS instructions that access local memory can only uses addresses that are less than or equal to the value of M0. When M0 is uninitialized, then we experience undefined behavior. This patch also changes the behavior to emit S_WQM_B64 on pixel shaders no matter what kind of DS instruction is used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201097 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: use natural LLVM IR for vshll instructionsTim Northover2014-02-10
| | | | | | | | Similarly to the vshrn instructions, these are simple zext/sext + trunc operations. Using normal LLVM IR should allow for better code, and more sharing with the AArch64 backend. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201093 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Handle aliases of conditional branches without b.pred form.Chad Rosier2014-02-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201091 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: r12 is callee-saved for interrupt handlersOliver Stannard2014-02-10
| | | | | | | | | For A- and R-class processors, r12 is not normally callee-saved, but is for interrupt handlers. See AAPCS, 5.3.1.1, "Use of IP by the linker". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201089 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: use LLVM IR to represent the vshrn operationTim Northover2014-02-10
| | | | | | | | | | vshrn is just the combination of a right shift and a truncate (and the limits on the immediate value actually mean the signedness of the shift doesn't matter). Using that representation allows us to get rid of an ARM-specific intrinsic, share more code with AArch64 and hopefully get better code out of the mid-end optimisers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201085 91177308-0d34-0410-b5e6-96231b3b80d8
* Test commit - added a new line to vec_shuf-insert.ll.Robert Lougher2014-02-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201083 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Add DLSA instruction.Matheus Almeida2014-02-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201081 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Update FileCheck prefix in preparation forMatheus Almeida2014-02-10
| | | | | | | | | the addition of Mips64 tests. No functional changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201080 91177308-0d34-0410-b5e6-96231b3b80d8
* [asan] support for FreeBSD, LLVM part. patch by Viktor KutuzovKostya Serebryany2014-02-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201067 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Fixed extract_vector_elt for v16i1 and v8i1 vectors.Elena Demikhovsky2014-02-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201066 91177308-0d34-0410-b5e6-96231b3b80d8
* Recommit r201059 and r201060 with hopefully a fix for its original failure.Craig Topper2014-02-10
| | | | | | | | | | | | Original commits messages: Add MRMXr/MRMXm form to X86 for use by instructions which treat the 'reg' field of modrm byte as a don't care value. Will allow for simplification of disassembler code. Simplify a bunch of code by removing the need for the x86 disassembler table builder to know about extended opcodes. The modrm forms are sufficient to convey the information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201065 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64]Implement the copy of two FPR8 registers by using FMOVss of two ↵Hao Liu2014-02-10
| | | | | | FPR32 registers in copyPhysReg. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201061 91177308-0d34-0410-b5e6-96231b3b80d8
* AsmParser: Parse (and ignore) nested .macro definitions.Benjamin Kramer2014-02-09
| | | | | | | | | This enables a slightly odd feature of gas. The macro is defined when the outermost macro is instantiated. PR18599 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201045 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: change attribute tests to use parsed formSaleem Abdulrasool2014-02-08
| | | | | | | | | This makes the tests more readable by using the -arm-attributes decoding support in llvm-readobj since that is now available. Change the invocation commands to be similar to other test and use a more precise triple (the tests only require ARM EABI support). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201029 91177308-0d34-0410-b5e6-96231b3b80d8
* LoopVectorizer: Keep track of conditional store basic blocksArnold Schwaighofer2014-02-08
| | | | | | | | | | | | | Before conditional store vectorization/unrolling we had only one vectorized/unrolled basic block. After adding support for conditional store vectorization this will not only be one block but multiple basic blocks. The last block would have the back-edge. I updated the code to use a vector of basic blocks instead of a single basic block and fixed the users to use the last entry in this vector. But, I forgot to add the basic blocks to this vector! Fixes PR18724. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201028 91177308-0d34-0410-b5e6-96231b3b80d8
* [Constant Hoisting] Fix insertion point for constant materialization.Juergen Ributzka2014-02-08
| | | | | | | | | | The bitcast instruction during constant materialization was not placed correcly in the presence of phi nodes. This commit fixes the insertion point to be in the idom instead. This fixes PR18768 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201009 91177308-0d34-0410-b5e6-96231b3b80d8
* Always create a temporary symbol to use with the cfi frame.Rafael Espindola2014-02-07
| | | | | | | This is a small simplification and a small step in fixing pr18743 since private functions on MachO should be using a 'l' prefix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200994 91177308-0d34-0410-b5e6-96231b3b80d8
* Use FileCheck variables to simplify this test.Rafael Espindola2014-02-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200992 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix Darwin bots from EHABI changeRenato Golin2014-02-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200990 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add failing test for 3 x i64 vectors.Matt Arsenault2014-02-07
| | | | | | | Stores of <4 x i64> do work (although they do expand to 4 stores instead of 2), but 3 x i64 vectors fail to select. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200989 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove -arm-disable-ehabi optionRenato Golin2014-02-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200988 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't internalize linkonce_odr non constant variables.Rafael Espindola2014-02-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200983 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Forbid the use of registers t6, t7 and t8 if the target is NaCl.Sasa Stankovic2014-02-07
| | | | | | | | Differential Revision: http://llvm-reviews.chandlerc.com/D2694 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200978 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a bug with .weak_def_can_be_hidden: Mutable variables cannot use it.Rafael Espindola2014-02-07
| | | | | | Thanks to John McCall for noticing it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200977 91177308-0d34-0410-b5e6-96231b3b80d8
* LLVM-1163: AAPCS-VFP violation when CPRC allocated to stackOliver Stannard2014-02-07
| | | | | | | | | | | | | | According to the AAPCS, when a CPRC is allocated to the stack, all other VFP registers should be marked as unavailable. I have also modified the rules for allocating non-CPRCs to the stack, to make it more explicit that all GPRs must be made unavailable. I cannot think of a case where the old version would produce incorrect answers, so there is no test for this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200970 91177308-0d34-0410-b5e6-96231b3b80d8
* Changed comment.Sasa Stankovic2014-02-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200969 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Add support for parsing synthetic instruction 'mov'. Venkatraman Govindaraju2014-02-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200965 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Emit correct encoding for atomic instructions. Also, add support for ↵Venkatraman Govindaraju2014-02-07
| | | | | | parsing CAS instructions to test the CAS encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200963 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Emit relocations for Thread Local Storage (TLS) when integrated ↵Venkatraman Govindaraju2014-02-07
| | | | | | assembler is used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200962 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Emit correct relocations for PIC code when integrated assembler is used.Venkatraman Govindaraju2014-02-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200961 91177308-0d34-0410-b5e6-96231b3b80d8
* PGO branch weight: fix PR18752.Manman Ren2014-02-07
| | | | | | | | Fix a bug triggered in IfConverterTriangle when CvtBB has multiple predecessors by getting the weights before removing a successor. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200958 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Resolve a long standing FIXME and properly isel pextr[bw].Jim Grosbach2014-02-07
| | | | | | | | | | | | | | | | | Generalize the AArch64 .td nodes for AssertZext and AssertSext. Use them to match the relevant pextr store instructions. The test widen_load-2.ll requires a slight change because with the stores gone, the remaining instructions are scheduled in a different order. Add test cases for SSE4 and AVX variants. Resolves rdar://13414672. Patch by Adam Nemet <anemet@apple.com>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200957 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert test to FileCheck.Rafael Espindola2014-02-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200955 91177308-0d34-0410-b5e6-96231b3b80d8
* [CodeGenPrepare] Move away sign extensions that get in the way of addressingQuentin Colombet2014-02-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | mode. Basically the idea is to transform code like this: %idx = add nsw i32 %a, 1 %sextidx = sext i32 %idx to i64 %gep = gep i8* %myArray, i64 %sextidx load i8* %gep Into: %sexta = sext i32 %a to i64 %idx = add nsw i64 %sexta, 1 %gep = gep i8* %myArray, i64 %idx load i8* %gep That way the computation can be folded into the addressing mode. This transformation is done as part of the addressing mode matcher. If the matching fails (not profitable, addressing mode not legal, etc.), the matcher will revert the related promotions. <rdar://problem/15519855> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200947 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add a MUBUF store pattern for Reg+Imm offsetsTom Stellard2014-02-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200935 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add a MUBUF store pattern for Imm offsetsTom Stellard2014-02-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200934 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add a MUBUF load pattern for Reg+Imm offsetsTom Stellard2014-02-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200933 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Use immediates offsets for SMRD instructions whenever possibleTom Stellard2014-02-06
| | | | | | | | There was a problem with the old pattern, so we were copying some larger immediates into registers when we could have been encoding them in the instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200932 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: add costs for 64-bit vector ext/trunc & rebalanceTim Northover2014-02-06
| | | | | | | | | | | | | | | | | | | | The most important part of this is probably adding any cost at all for operations like zext <8 x i8> to <8 x i32>. Before they were being recorded as extremely costly (24, I believe) which made LLVM fall back on a 4-wide vectorisation of a loop. It also rebalances the values for sext, zext and trunc. Lacking any other sane metric that might work across CPU microarchitectures I went for instructions. This seems to be in reasonable accord with the rest of the table (sitofp, ...) though no doubt at least one value is sub-optimal for some bizarre reason. Finally, separate AVX and AVX2 values are provided where appropriate. The CodeGen is quite different in many cases. rdar://problem/15981990 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200928 91177308-0d34-0410-b5e6-96231b3b80d8
* A memcpy out of an fresh alloca is a no-op, delete it. Patch by Patrick Walton!Nick Lewycky2014-02-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200907 91177308-0d34-0410-b5e6-96231b3b80d8
* [PM] Add a new "lazy" call graph analysis pass for the new pass manager.Chandler Carruth2014-02-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The primary motivation for this pass is to separate the call graph analysis used by the new pass manager's CGSCC pass management from the existing call graph analysis pass. That analysis pass is (somewhat unfortunately) over-constrained by the existing CallGraphSCCPassManager requirements. Those requirements make it *really* hard to cleanly layer the needed functionality for the new pass manager on top of the existing analysis. However, there are also a bunch of things that the pass manager would specifically benefit from doing differently from the existing call graph analysis, and this new implementation tries to address several of them: - Be lazy about scanning function definitions. The existing pass eagerly scans the entire module to build the initial graph. This new pass is significantly more lazy, and I plan to push this even further to maximize locality during CGSCC walks. - Don't use a single synthetic node to partition functions with an indirect call from functions whose address is taken. This node creates a huge choke-point which would preclude good parallelization across the fanout of the SCC graph when we got to the point of looking at such changes to LLVM. - Use a memory dense and lightweight representation of the call graph rather than value handles and tracking call instructions. This will require explicit update calls instead of some updates working transparently, but should end up being significantly more efficient. The explicit update calls ended up being needed in many cases for the existing call graph so we don't really lose anything. - Doesn't explicitly model SCCs and thus doesn't provide an "identity" for an SCC which is stable across updates. This is essential for the new pass manager to work correctly. - Only form the graph necessary for traversing all of the functions in an SCC friendly order. This is a much simpler graph structure and should be more memory dense. It does limit the ways in which it is appropriate to use this analysis. I wish I had a better name than "call graph". I've commented extensively this aspect. This is still very much a WIP, in fact it is really just the initial bits. But it is about the fourth version of the initial bits that I've implemented with each of the others running into really frustrating problms. This looks like it will actually work and I'd like to split the actual complexity across commits for the sake of my reviewers. =] The rest of the implementation along with lots of wiring will follow somewhat more rapidly now that there is a good path forward. Naturally, this doesn't impact any of the existing optimizer. This code is specific to the new pass manager. A bunch of thanks are deserved for the various folks that have helped with the design of this, especially Nick Lewycky who actually sat with me to go through the fundamentals of the final version here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200903 91177308-0d34-0410-b5e6-96231b3b80d8
* [DAG] Don't pull the binary operation though the shift if the operands have ↵Juergen Ributzka2014-02-06
| | | | | | | | | | | | opaque constants. During DAGCombine visitShiftByConstant assumes that certain binary operations with only constant operands can always be folded successfully. This is no longer true when the constant is opaque. This commit fixes visitShiftByConstant by not performing the optimization for opaque constants. Otherwise we would end up in an infinite DAGCombine loop. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200900 91177308-0d34-0410-b5e6-96231b3b80d8
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