summaryrefslogtreecommitdiff
path: root/lib
Commit message (Collapse)AuthorAge
* Revert r207571 - Add slp vectorization to LTO passesYi Jiang2014-04-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207693 91177308-0d34-0410-b5e6-96231b3b80d8
* [X86] Never hoist the shift value of a shift instruction.Michael Zolotukhin2014-04-30
| | | | | | | | | | | There is no need to check if we want to hoist the immediate value of an shift instruction. Simply return TCC_Free right away. This change is like r206101, but for X86. rdar://problem/16190769 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207692 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert several loops over MachineFunction basic blocks to range-based loopsAlexey Samsonov2014-04-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207683 91177308-0d34-0410-b5e6-96231b3b80d8
* [IPO/MergeFunctions] changes so it doesn't try to bitcast a struct return ↵Carlo Kok2014-04-30
| | | | | | type but instead recreates it with insert/extract value. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207679 91177308-0d34-0410-b5e6-96231b3b80d8
* IR: Conservatively verify inalloca argumentsDavid Majnemer2014-04-30
| | | | | | | | | | | | Summary: Try to spot obvious mismatches with inalloca use. Reviewers: rnk Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D3572 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207676 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify ELFObjectWriter::SymbolValue.Rafael Espindola2014-04-30
| | | | | | It now defers all offset computation to getSymbolOffset. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207674 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Add instruction alias (negu).Matheus Almeida2014-04-30
| | | | | | | | | | | | Summary: negu $reg is equivalent to negu $reg, $reg. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3510 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207673 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Add instruction alias (sltu).Matheus Almeida2014-04-30
| | | | | | | | | | | | | | Summary: The pattern sltu $r1, $r2, $imm is found in handwritten assembly which is just a shorthand version of sltui $r1, $r2, $imm. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3508 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207671 91177308-0d34-0410-b5e6-96231b3b80d8
* ELFObjectWriter: deduplicate suffices in strtabHans Wennborg2014-04-30
| | | | | | | | | | | | | | | We already do this for shstrtab, so might as well do it for strtab. This extracts the string table building code into a separate class. The idea is to use it for other object formats too. I mostly wanted to do this for the general principle, but it does save a little bit on object file size. I tried this on a clang bootstrap and saved 0.54% on the sum of object file sizes (1.14 MB out of 212 MB for a release build). Differential Revision: http://reviews.llvm.org/D3533 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207670 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: print fp immediates without using scientific notation.Tim Northover2014-04-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207669 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: implement remaining TLS relocations (purely MC).Tim Northover2014-04-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207668 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: add specific diagnostic for MRS/MSR and enable tests.Tim Northover2014-04-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207667 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: accept and print floating-point immediate 0 as "#0.0"Tim Northover2014-04-30
| | | | | | | | | | It's been decided that in the future, the floating-point immediate in instructions like "fcmeq v0.2s, v1.2s, #0.0" will be canonically "0.0", which has been implemented on AArch64 already but not ARM64. This fixes that issue. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207666 91177308-0d34-0410-b5e6-96231b3b80d8
* IR: Alloca clones should remember inalloca stateDavid Majnemer2014-04-30
| | | | | | | | | Pretty straightforward, we weren't propagating whether or not an AllocaInst had 'inalloca' marked on it when it came time to clone it. The inliner exposed this bug. A reduced testcase is forthcoming. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207665 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Add instruction alias (dsll and dsrl).Matheus Almeida2014-04-30
| | | | | | | | | | | | | | Summary: The pattern dsll/dsrl $rd, $rt, $rs is found in handwritten assembly which is just a shorthand version of dsllv/dsrlv $rd, $rt, $rs. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3486 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207664 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Use VALU instructions for copying i1 valuesTom Stellard2014-04-30
| | | | | | | | | We can't use SALU instructions for this since they ignore the EXEC mask and are always executed. This fixes several OpenCV tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207661 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Teach moveToVALU how to handle some SMRD instructionsTom Stellard2014-04-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207660 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM64][fast-isel] Fast-isel doesn't know how to handle f128.Chad Rosier2014-04-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207659 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Add instruction alias (sll and srl).Matheus Almeida2014-04-30
| | | | | | | | | | | | | | Summary: The pattern sll/srl $rd, $rt, $rs is found in handwritten assembly which is just a shorthand version of sllv/srlv $rd, $rt, $rs. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3483 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207657 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix MipsLongBranch pass to work when the offset from the branch to theSasa Stankovic2014-04-30
| | | | | | | | | | | | | | | target cannot be determined accurately. This is the case for NaCl where the sandboxing instructions are added in MC layer, after the MipsLongBranch pass. It is also the case when the code has inline assembly. Instead of calculating offset in the MipsLongBranch pass, use %hi(sym1 - sym2) and %lo(sym1 - sym2) expressions that are resolved during the fixup. This patch also deletes microMIPS test file test/CodeGen/Mips/micromips-long-branch.ll and implements microMIPS CHECKs in a much simpler way in a file test/CodeGen/Mips/longbranch.ll, together with MIPS32 and MIPS64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207656 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Remove unused function AMDGPUSubtarget::getDefaultSize()Tom Stellard2014-04-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207654 91177308-0d34-0410-b5e6-96231b3b80d8
* [asan] Disable asm instrumentation on unsupported platforms.Evgeniy Stepanov2014-04-30
| | | | | | | | | | Only emit calls to compiler-rt asm routines on platforms where they are present (currently limited to linux i386/x86_64). Patch by Yuri Gorshenin. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207651 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: print lsr instead of lsrv for variable shifts (etc)Tim Northover2014-04-30
| | | | | | | The canonical syntax for shifts by a variable amount does not end with 'v', but that syntax should be supported as an alias (presumably for legacy reasons). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207649 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: use 32-bit operations for uxtb & uxthTim Northover2014-04-30
| | | | | | Testing will be enabled shortly with basic-a64-instructions.s git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207648 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: allow smaller granule relocations on MOVZ/MOVNTim Northover2014-04-30
| | | | | | Testing will be enabled shortly with basic-a64-instructions.s git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207647 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: copy support for bCC instead of b.CC across.Tim Northover2014-04-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207646 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: expunge CPSR from the sourcesTim Northover2014-04-30
| | | | | | | | | | | | AArch64 does not have a CPSR register in the same way that AArch32 does. Most of its compiler-relevant roles have been taken over by the more specific NZCV register (representing just the flags set by normal instructions). Its system control functions still remain, but are now under the pseudo-register referred to as "PSTATE". They're accessed via various MRS & MSR instructions described in the reference manual. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207645 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: use HS instead of CS & LO instead of CC.Tim Northover2014-04-30
| | | | | | | | | On instructions using the NZCV register, a couple of conditions have dual representations: HS/CS and LO/CC (meaning unsigned-higher-or-same/carry-set and unsigned-lower/carry-clear). The first of these is more descriptive in most circumstances, so we should print it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207644 91177308-0d34-0410-b5e6-96231b3b80d8
* Grammar fix.Rafael Espindola2014-04-30
| | | | | | Thanks to Saleem Abdulrasool for noticing it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207643 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Fix vector insertions where the index is variableDaniel Sanders2014-04-30
| | | | | | | | | | | | | | | | | | | | | Summary: This isn't supported directly so we rotate the vector by the desired number of elements, insert to element zero, then rotate back. The i64 case generates rather poor code on MIPS32. There is an obvious optimisation to be made in future (do both insert.w's inside a shared rotate/unrotate sequence) but for now it's sufficient to select valid code instead of aborting. Depends on D3536 Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://reviews.llvm.org/D3537 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207640 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: accept ELF-relocated load/store insts without a #.Tim Northover2014-04-30
| | | | | | | E.g. we print "ldr x0, [x0, :lo12:symbol]" so we need to accept that syntax too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207639 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: remove duplication by templating InstPrinter methodsTim Northover2014-04-30
| | | | | | No functional change, so no tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207638 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Add support for .cpload.Matheus Almeida2014-04-30
| | | | | | | | | | | | | | | | | | | | Summary: This directive is used for setting up $gp in the beginning of a function. It expands to three instructions if PIC is enabled: lui $gp, %hi(_gp_disp) addui $gp, $gp, %lo(_gp_disp) addu $gp, $gp, $reg _gp_disp is a special symbol that the linker sets to the distance between the lui instruction and the context pointer (_gp). Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3480 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207637 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: use hex immediates for movz/movk instructionsTim Northover2014-04-30
| | | | | | | | Since these are mostly used in "lsl #16", "lsl #32", "lsl #48" combinations to piece together an immediate in 16-bit chunks, hex is probably the most appropriate format. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207635 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: hexify printing various immediate operandsTim Northover2014-04-30
| | | | | | | | | | This is mostly aimed at the NEON logical operations and MOVI/MVNI (since they accept weird shifts which are more naturally understandable in hex notation). Also changes BRK/HINT etc, which is probably a neutral change, but easier than the alternative. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207634 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: print canonical syntax for add/sub (imm) instructions.Tim Northover2014-04-30
| | | | | | | | | | Since these instructions only accept a 12-bit immediate, possibly shifted left by 12, the canonical syntax used by the architecture reference manual is "#N {, lsl #12 }". We should accept an immediate that has already been shifted, (e.g. Also, print a comment giving the full addend since it can be helpful. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207633 91177308-0d34-0410-b5e6-96231b3b80d8
* [LCG] Add the really, *really* boring edge insertion case: adding anChandler Carruth2014-04-30
| | | | | | | | | | edge entirely within an existing SCC. Shockingly, making the connected component more connected is ... a total snooze fest. =] Anyways, its wired up, and I even added a test case to make sure it pretty much sorta works. =D git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207631 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM64] Simplify if condition.James Molloy2014-04-30
| | | | | | | v2f32 and v4f32 were missed out of these conditions, so this is also a bugfix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207628 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM64] Fix stupid copy-pasto in ARM64MCAsmInfo.cpp - aarch64_be -> arm64_beJames Molloy2014-04-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207627 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM64] Try and make the ELF MCJIT *slightly* less broken for ARM64.James Molloy2014-04-30
| | | | | | | | | A bunch of switch cases were missing, not just for ARM64 but also for AArch64_BE. I've fixed all those, but there's zero testing as ExecutionEngine tests are disabled when crosscompiling and I don't have a native platform available to test on. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207626 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM64] Ensure arm64_be is dealt with when emitting debug info.James Molloy2014-04-30
| | | | | | | This is a partial port of r204816 (cpirker "Elf support for MC-JIT runtime dynamic linker") from AArch64 to ARM64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207625 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: make sure FastISel uses a GPR64 source in 64-bit extensions.Tim Northover2014-04-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207620 91177308-0d34-0410-b5e6-96231b3b80d8
* [LCG] Actually test the *basic* edge removal bits (IE, the non-SCCChandler Carruth2014-04-30
| | | | | | | | | | | | | | | | | | | | | | | | | | bits), and discover that it's totally broken. Yay tests. Boo bug. Fix the basic edge removal so that it works by nulling out the removed edges rather than actually removing them. This leaves the indices valid in the map from callee to index, and preserves some of the locality for iterating over edges. The iterator is made bidirectional to reflect that it now has to skip over null entries, and the skipping logic is layered onto it. As future work, I would like to track essentially the "load factor" of the edge list, and when it falls below a threshold do a compaction. An alternative I considered (and continue to consider) is storing the callees in a doubly linked list where each element of the list is in a set (which is essentially the classical linked-hash-table datastructure). The problem with that approach is that either you need to heap allocate the linked list nodes and use pointers to them, or use a bucket hash table (with even *more* linked list pointer overhead!), etc. It's pretty easy to get 5x overhead for values that are just pointers. So far, I think punching holes in the vector, and periodic compaction is likely to be much more efficient overall in the space/time tradeoff. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207619 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a <tuple> include to more files that aren't getting it transitively on MSVC.Benjamin Kramer2014-04-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207617 91177308-0d34-0410-b5e6-96231b3b80d8
* Use makeArrayRef insted of calling ArrayRef<T> constructor directly. I ↵Craig Topper2014-04-30
| | | | | | introduced most of these recently. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207616 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: support stack probe emission for Windows on ARMSaleem Abdulrasool2014-04-30
| | | | | | | | | | | | | | | | | This introduces the stack lowering emission of the stack probe function for Windows on ARM. The stack on Windows on ARM is a dynamically paged stack where any page allocation which crosses a page boundary of the following guard page will cause a page fault. This page fault must be handled by the kernel to ensure that the page is faulted in. If this does not occur and a write access any memory beyond that, the page fault will go unserviced, resulting in an abnormal program termination. The watermark for the stack probe appears to be at 4080 bytes (for accommodating the stack guard canaries and stack alignment) when SSP is enabled. Otherwise, the stack probe is emitted on the page size boundary of 4096 bytes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207615 91177308-0d34-0410-b5e6-96231b3b80d8
* ConstantHoisting.cpp: Add <tuple> for std::tie, since r207593 removed ↵NAKAMURA Takumi2014-04-30
| | | | | | FileSystem.h, it includes <tuple>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207614 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: print COFF function header for Windows on ARMSaleem Abdulrasool2014-04-30
| | | | | | | | | Emit the COFF header when printing out the function. This is important as the header contains two important pieces of information: the storage class for the symbol and the symbol type information. This bit of information is required for the linker to correctly identify the type of symbol that it is dealing with. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207613 91177308-0d34-0410-b5e6-96231b3b80d8
* De-virtualize or remove some methods that have no overrides nor override ↵Craig Topper2014-04-30
| | | | | | anything. In some cases remove all together if there are no callers either. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207610 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: move llvm_unreachable useSaleem Abdulrasool2014-04-30
| | | | | | | | When building with -Werror=covered-switch-default (as on the buildbots), the build would fail since all cases are covered by the switch. Move the llvm_unreachable to the end of the function as an annotation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207609 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3 (git 2.25.1) at 2024-04-28 16:46:12 +0000