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* This was a nifty test, but remove it.Sean Silva2013-06-21
| | | | | | | | | | | | | | It wouldn't really test anything that doesn't already have a more targeted test: `yaml2obj-elf-section-basic.yaml`: Already tests that section content is correctly passed though. `yaml2obj-elf-symbol-basic.yaml` (this file): Tests that the st_value and st_size attributes of `main` are set correctly. Between those two tests, disassembling the file doesn't really add anything, so just remove mention of disassembling the file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184607 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Put r184469 disassembler test back on X86"Sean Silva2013-06-21
| | | | | | | | | This reverts commit r184602. In an upcoming commit, I will just remove the disassembler part of the test; it was mostly just a "nifty" thing marking a milestone but it doesn't test anything that isn't tested elsewhere. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184606 91177308-0d34-0410-b5e6-96231b3b80d8
* DebugInfo: Don't lose unreferenced non-trivial by-value parametersDavid Blaikie2013-06-21
| | | | | | | | | | | | A FastISel optimization was causing us to emit no information for such parameters & when they go missing we end up emitting a different function type. By avoiding that shortcut we not only get types correct (very important) but also location information (handy) - even if it's only live at the start of a function & may be clobbered later. Reviewed/discussion by Evan Cheng & Dan Gohman. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184604 91177308-0d34-0410-b5e6-96231b3b80d8
* Put r184469 disassembler test back on X86Renato Golin2013-06-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184602 91177308-0d34-0410-b5e6-96231b3b80d8
* [yaml2obj][ELF] Don't do disassembly in this test.Sean Silva2013-06-21
| | | | | | | | | This was causing buildbot failures when build without X86 support. Is there a way to conditionalize the test on the X86 target being present? git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184597 91177308-0d34-0410-b5e6-96231b3b80d8
* Add '-mcpu=' to prevent breaking on ATOM due to different code scheduleMichael Liao2013-06-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184591 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "BlockFrequency: Saturate at 1 instead of 0 when multiplying a ↵Benjamin Kramer2013-06-21
| | | | | | | | frequency with a branch probability." This reverts commit r184584. Breaks PPC selfhost. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184590 91177308-0d34-0410-b5e6-96231b3b80d8
* BlockFrequency: Saturate at 1 instead of 0 when multiplying a frequency with ↵Benjamin Kramer2013-06-21
| | | | | | | | | | | | | | | a branch probability. Zero is used by BlockFrequencyInfo as a special "don't know" value. It also causes a sink for frequencies as you can't ever get off a zero frequency with more multiplies. This recovers a 10% regression on MultiSource/Benchmarks/7zip. A zero frequency was propagated into an inner loop causing excessive spilling. PR16402. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184584 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Add support for selecting CUDA vs OCL mode based on tripleJustin Holewinski2013-06-21
| | | | | | IR for CUDA should use "nvptx[64]-nvidia-cuda", and IR for NV OpenCL should use "nvptx[64]-nvidia-nvcl" git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184579 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing REQUIRES: asserts in crash.ll.Andrew Trick2013-06-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184576 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR16360Michael Liao2013-06-21
| | | | | | | | | When (srl (anyextend x), c) is folded into (anyextend (srl x, c)), the high bits are not cleared. Add 'and' to clear off them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184575 91177308-0d34-0410-b5e6-96231b3b80d8
* Update physreg live intervals during remat.Andrew Trick2013-06-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184574 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Support R_PPC_REL16 family of relocationsUlrich Weigand2013-06-21
| | | | | | | | | | | | | The GNU assembler supports (as extension to the ABI) use of PC-relative relocations in half16 fields, which allows writing code like: li 1, base-. This patch adds support for those relocation types in the assembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184552 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Support various tls-related modifiersUlrich Weigand2013-06-21
| | | | | | | | | | | | The current code base only supports the minimum set of tls-related relocations and @modifiers that are necessary to support compiler- generated code. This patch extends this to the full set defined in the ABI (and supported by the GNU assembler) for the benefit of the assembler parser. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184551 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Support @higher et.al. modifiersUlrich Weigand2013-06-21
| | | | | | | | | This adds support for the @higher, @highera, @highest, and @highesta modifers, including some missing relocation types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184550 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Support @toc@h modifierUlrich Weigand2013-06-21
| | | | | | | | | This adds the relocation type and other necessary infrastructure to use the @toc@h modifier in the assembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184549 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Support @h modifierUlrich Weigand2013-06-21
| | | | | | | | | | | | | | This adds necessary infrastructure to support the @h modifier. Note that all required relocation types were already present (and unused). This patch provides support for using @h in the assembler; it would also be possible to now use this feature in code generated by the compiler, but this is not done yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184548 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix an ordering problem in the test.Manuel Klimek2013-06-21
| | | | | | | | | The output can be in different orders, which breaks the test in some situations. I have not yet found out what the root cause of the order difference is. This fixes our internal build. If it is not the right solution, feel free to roll back. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184535 91177308-0d34-0410-b5e6-96231b3b80d8
* [yaml2obj][ELF] Allow expressing undefined symbols.Sean Silva2013-06-21
| | | | | | | | | | Previously we unconditionally enforced that section references in symbols in the YAML had a name that was a section name present in the object, and linked the references to that section. Now, permit empty section names (already the default, if the `Section` key is not provided) to indicate SHN_UNDEF. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184513 91177308-0d34-0410-b5e6-96231b3b80d8
* [yaml2obj][ELF] Don't explicitly set `Binding` with STB_*Sean Silva2013-06-21
| | | | | | | | | | | | | | | Instead, just have 3 sub-lists, one for each of {STB_LOCAL,STB_GLOBAL,STB_WEAK}. This allows us to be a lot more explicit w.r.t. the symbol ordering in the object file, because if we allowed explicitly setting the STB_* `Binding` key for the symbol, then we might have ended up having to shuffle STB_LOCAL symbols to the front of the list, which is likely to cause confusion and potential for error. Also, this new approach is simpler ;) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184506 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Remove a (false) dependency on the memoryoperand's value as we do not useQuentin Colombet2013-06-20
| | | | | | | | | | | it at the moment. This allows to form more paired loads even when stack coloring pass destroys the memoryoperand's value. <rdar://problem/13978317> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184492 91177308-0d34-0410-b5e6-96231b3b80d8
* Update the X86 disassembler to use xacquire and xrelease when appropriate.Kevin Enderby2013-06-20
| | | | | | | | | | | | | | | | | | This is a bit tricky as the xacquire and xrelease hints use the same bytes, 0xf2 and 0xf3, as the repne and rep prefixes. Fortunately llvm has different llvm MCInst Opcode enums for rep/xrelease and repne/xacquire. So to make this work a boolean was added the InternalInstruction struct as part of the Prefix state which is set with the added logic in readPrefixes() when decoding an instruction to determine if these prefix bytes are to be disassembled as xacquire or xrelease. Then we let the matcher pick the normal prefix instructionID and we change the Opcode after that when it is set into the MCInst being created. rdar://11019859 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184490 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Expand sub for v2i32 and v4i32 for SITom Stellard2013-06-20
| | | | | | | | | | | Also add a v2i32 test to the existing v4i32 test. Patch by: Aaron Watry Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Aaron Watry<awatry@gmail.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184482 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Expand add for v2i32 and v4i32Tom Stellard2013-06-20
| | | | | | | | | | | | Also add SI tests to existing file and a v2i32 test for both R600 and SI. Patch by: Aaron Watry Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Aaron Watry <awatry@gmail.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184481 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Expand v2i32 load/store instead of custom loweringTom Stellard2013-06-20
| | | | | | | | | | | | | | The custom lowering causes llc to crash with a segfault. Ideally, the custom lowering can be fixed, but this allows programs which load/store v2i32 to work without crashing. Patch by: Aaron Watry Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Aaron Watry<awatry@gmail.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184480 91177308-0d34-0410-b5e6-96231b3b80d8
* [yaml2obj][ELF] Add support for st_value and st_size.Sean Silva2013-06-20
| | | | | | | | | After this patch, the ELF file produced by `yaml2obj-elf-symbol-basic.yaml`, when linked and executed on x86_64 (under SysV ABI, obviously; I tested on Linux), produces a working executable that goes into an infinite loop! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184469 91177308-0d34-0410-b5e6-96231b3b80d8
* [yaml2obj][ELF] Allow symbols to reference sections.Sean Silva2013-06-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184468 91177308-0d34-0410-b5e6-96231b3b80d8
* Use only the filename when deciding if a file is a duplicate.Rafael Espindola2013-06-20
| | | | | | Matches gnu ar behavior. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184448 91177308-0d34-0410-b5e6-96231b3b80d8
* This reverts r155000.Joey Gouly2013-06-20
| | | | | | | | | | The cdp2 instruction should have the same restrictions as cdp on the co-processor registers. VFP instructions on v8/AArch32 share the same encoding space as cdp2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184445 91177308-0d34-0410-b5e6-96231b3b80d8
* SLPVectorization: Add a basic support for cross-basic block slp vectorization.Nadav Rotem2013-06-20
| | | | | | | | | We collect gather sequences when we vectorize basic blocks. Gather sequences are excellent hints for vectorization of other basic blocks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184444 91177308-0d34-0410-b5e6-96231b3b80d8
* Give this X86-specific test a triple so it's actually X86-specific.David Blaikie2013-06-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184443 91177308-0d34-0410-b5e6-96231b3b80d8
* [MC] Support @ variants with directional labelsUlrich Weigand2013-06-20
| | | | | | | | | | | | | The assembler parser common code supports recognizing symbol variants using the @ modifer. On PowerPC, it should also be possible to use (some of) those modifiers with directional labels, like "1f@l". This patch adds support for accepting symbol variants on directional labels as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184437 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Optimize @ha/@l constructsUlrich Weigand2013-06-20
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for having the assembler optimize fixups to constructs like "symbol@ha" or "symbol@l" if "symbol" can be resolved at assembler time. This optimization is already present in the PPCMCExpr.cpp code for handling PPC_HA16/PPC_LO16 target expressions. However, those target expression were used only on Darwin targets. This patch changes target expression code so that they are usable also with the GNU assembler (using the @ha / @l syntax instead of the ha16() / lo16() syntax), and changes the MCInst lowering code to generate those target expressions where appropriate. It also changes the asm parser to generate HA16/LO16 target expressions when parsing assembler source that uses the @ha / @l modifiers. The effect is that now the above- mentioned optimization automatically becomes available for those situations too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184436 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Support compare mnemonics with implied CR0Ulrich Weigand2013-06-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Just like for branch mnemonics (where support was recently added), the assembler is supposed to support extended mnemonics for the compare instructions where no condition register is specified explicitly (and CR0 is assumed implicitly). This patch adds support for those extended compare mnemonics. Index: llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s =================================================================== --- llvm-head.orig/test/MC/PowerPC/ppc64-encoding-ext.s +++ llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s @@ -449,21 +449,37 @@ # CHECK: cmpdi 2, 3, 128 # encoding: [0x2d,0x23,0x00,0x80] cmpdi 2, 3, 128 +# CHECK: cmpdi 0, 3, 128 # encoding: [0x2c,0x23,0x00,0x80] + cmpdi 3, 128 # CHECK: cmpd 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x00] cmpd 2, 3, 4 +# CHECK: cmpd 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x00] + cmpd 3, 4 # CHECK: cmpldi 2, 3, 128 # encoding: [0x29,0x23,0x00,0x80] cmpldi 2, 3, 128 +# CHECK: cmpldi 0, 3, 128 # encoding: [0x28,0x23,0x00,0x80] + cmpldi 3, 128 # CHECK: cmpld 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x40] cmpld 2, 3, 4 +# CHECK: cmpld 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x40] + cmpld 3, 4 # CHECK: cmpwi 2, 3, 128 # encoding: [0x2d,0x03,0x00,0x80] cmpwi 2, 3, 128 +# CHECK: cmpwi 0, 3, 128 # encoding: [0x2c,0x03,0x00,0x80] + cmpwi 3, 128 # CHECK: cmpw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x00] cmpw 2, 3, 4 +# CHECK: cmpw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x00] + cmpw 3, 4 # CHECK: cmplwi 2, 3, 128 # encoding: [0x29,0x03,0x00,0x80] cmplwi 2, 3, 128 +# CHECK: cmplwi 0, 3, 128 # encoding: [0x28,0x03,0x00,0x80] + cmplwi 3, 128 # CHECK: cmplw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x40] cmplw 2, 3, 4 +# CHECK: cmplw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x40] + cmplw 3, 4 # FIXME: Trap mnemonics Index: llvm-head/lib/Target/PowerPC/PPCInstrInfo.td =================================================================== --- llvm-head.orig/lib/Target/PowerPC/PPCInstrInfo.td +++ llvm-head/lib/Target/PowerPC/PPCInstrInfo.td @@ -2201,3 +2201,12 @@ defm : BranchExtendedMnemonic<"ne", 68>; defm : BranchExtendedMnemonic<"nu", 100>; defm : BranchExtendedMnemonic<"ns", 100>; +def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>; +def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>; +def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>; +def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>; +def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm:$imm)>; +def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>; +def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm:$imm)>; +def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>; + git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184435 91177308-0d34-0410-b5e6-96231b3b80d8
* Make sure ar is creating a new file instead of updating an existing one.Rafael Espindola2013-06-20
| | | | | | Should fix the bots that are seeing a corrupted file from a previous run. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184424 91177308-0d34-0410-b5e6-96231b3b80d8
* Add r184420 back, but also handle long file names.Rafael Espindola2013-06-20
| | | | | | | | | | Original message: Don't include directory names in archives. This matches the behavior of both gnu and os x versions of ar. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184423 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Don't include directory names in archives."Rafael Espindola2013-06-20
| | | | | | | This reverts commit 184420. Investigating the bot failures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184421 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't include directory names in archives.Rafael Espindola2013-06-20
| | | | | | This matches the behavior of both gnu and os x versions of ar. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184420 91177308-0d34-0410-b5e6-96231b3b80d8
* Optimize register parsing for MipsAsmParser. Allow symbolic aliases for FPU ↵Vladimir Medic2013-06-20
| | | | | | registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184411 91177308-0d34-0410-b5e6-96231b3b80d8
* DebugInfo: don't use location lists when the location covers the whole ↵David Blaikie2013-06-20
| | | | | | | | | | | | | function anyway Fix up three tests - one that was relying on abbreviation number, another relying on a location list in this case (& testing raw asm, changed that to use dwarfdump on the debug_info now that that's where the location is), and another which was added in r184368 - exposing a bug in that fix that is exposed when we emit the location inline rather than through a location list. Fix that bug while I'm here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184387 91177308-0d34-0410-b5e6-96231b3b80d8
* Spelling correctionDavid Blaikie2013-06-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184370 91177308-0d34-0410-b5e6-96231b3b80d8
* DebugInfo: PR14763/r183329 correct the location of indirect parametersDavid Blaikie2013-06-19
| | | | | | | | | | | | | | | | We had been papering over a problem with location info for non-trivial types passed by value by emitting their type as references (this caused the debugger to interpret the location information correctly, but broke the type of the function). r183329 corrected the type information but lead to the debugger interpreting the pointer parameter as the value - the debug info describing the location needed an extra dereference. Use a new flag in DIVariable to add the extra indirection (either by promoting an existing DW_OP_reg (parameter passed in a register) to DW_OP_breg + 0 or by adding DW_OP_deref to an existing DW_OP_breg + n (parameter passed on the stack). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184368 91177308-0d34-0410-b5e6-96231b3b80d8
* Spell correct (s/begining/beginning/)David Blaikie2013-06-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184362 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm-dwarfdump: Add support for dumping the .debug_loc sectionDavid Blaikie2013-06-19
| | | | | | | | | This is a basic implementation - we still don't have any support (that I know of) for dumping DWARF expressions in a meaningful way, so the location information itself is just printed as a sequence of bytes as we do elsewhere. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184361 91177308-0d34-0410-b5e6-96231b3b80d8
* [MC/DWARF] Generate multiple .debug_line entries for adjacent .loc directivesUlrich Weigand2013-06-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | The compiler occasionally generates multiple .loc directives in a row (at the same instruction address). These need to be transformed into multple actual .debug_line table entries, since they are used to signal certain information to the debugger (e.g. if the opening brace of a function body is on the same line as the declaration). The MCAsmStreamer version of EmitDwarfLocDirective handles this correctly by emitting a .loc directive every time it is called. However, the MCObjectStream version simply defaults to recording the information and emitting only a single table entry later, e.g. when EmitInstruction is called. This patch introduces a MCAsmStreamer::EmitDwarfLocDirective version that emits a line table entry for a .loc directive that may already be pending before recording the new directive. (This is similar to how this is handled in GNU as.) With this patch (and the code alignment factor patch) applied, I'm now getting identical DWARF .debug sections for all test-suite object files on PowerPC for the internal and the external assembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184357 91177308-0d34-0410-b5e6-96231b3b80d8
* Move StructurizeCFG out of R600 to generic Transforms.Matt Arsenault2013-06-19
| | | | | | Register it with PassManager git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184343 91177308-0d34-0410-b5e6-96231b3b80d8
* LSR: Fix the parameters used to compute the scaling factor cost.Quentin Colombet2013-06-19
| | | | | | | | | | | | | | Prior to this change, the considered addressing modes may be invalid since the maximum and minimum offsets were not taking into account. This was causing an assertion failure. The added test case exercices that behavior. <rdar://problem/14199725> Assertion failed: (CurScaleCost >= 0 && "Legal addressing mode has an illegal cost!") git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184341 91177308-0d34-0410-b5e6-96231b3b80d8
* SLPVectorizer: handle scalars that are extracted from vectors (using ↵Nadav Rotem2013-06-19
| | | | | | ExtractElementInst). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184325 91177308-0d34-0410-b5e6-96231b3b80d8
* SLPVectorizer: start constructing chains at stores that are not power of two.Nadav Rotem2013-06-19
| | | | | | | | | | The type <3 x i8> is a common in graphics and we want to be able to vectorize it. This changes accelerates bullet by 12% and 471_omnetpp by 5%. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184317 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the 'R' modifier.Rafael Espindola2013-06-19
| | | | | | | It is not present in GNU or OS X versions and doesn't make a lot of sense for llvm-ar. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184306 91177308-0d34-0410-b5e6-96231b3b80d8
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