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path: root/lib/Target/ARM/ARMScheduleV6.td
Commit message (Expand)AuthorAge
* Tidy up. Trailing whitespace.Jim Grosbach2014-04-03
* Fix a number of problems with ARM fused multiply add/subtract instructions.Evan Cheng2012-04-11
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,...Jia Liu2012-02-18
* Sorry, several patches in one.Evan Cheng2011-01-20
* Conditional moves are slightly more expensive than moves.Evan Cheng2010-11-13
* putback r116983 and fix simple-fp-encoding.ll testsAndrew Trick2010-10-21
* Revert r116983, which is breaking all the buildbots.Owen Anderson2010-10-21
* Add missing scheduling itineraries for transfers between core registers and V...Evan Cheng2010-10-21
* Model operand cycles of vldm / vstm; also fixes scheduling itineraries of vld...Evan Cheng2010-10-07
* - Add TargetInstrInfo::getOperandLatency() to compute operand latencies. ThisEvan Cheng2010-10-06
* ARM instruction itinerary fixes:Evan Cheng2010-09-30
* Separate itinerary classes for mvn from mov; for tst / teq from cmp / cmn.Evan Cheng2010-09-29
* Assign bitwise binary instructions different itinerary classes from ALU instr...Evan Cheng2010-09-29
* Add support to model pipeline bypass / forwarding.Evan Cheng2010-09-28
* Remove a unused instruction itinerary class.Evan Cheng2010-09-25
* Fix zero and sign extension instructions scheduling itineraries.Evan Cheng2010-09-25
* More pseudo instruction scheduling itinerary fixes.Evan Cheng2010-09-24
* For each instruction itinerary class, specify the number of micro-ops eachEvan Cheng2010-09-09
* Clean up 80 column violations. No functional change.Jim Grosbach2010-06-02
* Make processor FUs unique for given itinerary. This extends the limit of 32Anton Korobeynikov2010-04-18
* Add ARMv6 itineraries.David Goodwin2009-11-18
* Checkpoint NEON scheduling itineraries.David Goodwin2009-09-23
* Add Cortex-A8 VFP model.David Goodwin2009-09-21
* Update Cortex-A8 instruction itineraries for integer instructions.David Goodwin2009-08-19
* Turn on if-conversion for thumb2.Evan Cheng2009-08-15
* Finalize itineraries for cortex-a8 integer multiplyDavid Goodwin2009-08-13
* Allow a zero cycle stage to reserve/require a FU without advancing the cycle ...David Goodwin2009-08-11
* Checkpoint scheduling itinerary changes.David Goodwin2009-08-10
* Fix comment.Evan Cheng2009-07-21
* Latency information for ARM v6. It's rough and not yet hooked up. Right now ...Evan Cheng2009-06-19
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