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* Tidy up. Trailing whitespace.Jim Grosbach2014-04-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205583 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a number of problems with ARM fused multiply add/subtract instructions.Evan Cheng2012-04-11
| | | | | | | | | | | 1. The new instruction itinerary entries are not properly described. 2. The asm parser can't handle vfms and vfnms. 3. There were no assembler, disassembler test cases. 4. HasNEON2 has the wrong assembler predicate. rdar://10139676 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154456 91177308-0d34-0410-b5e6-96231b3b80d8
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-18
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
* Sorry, several patches in one.Evan Cheng2011-01-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | TargetInstrInfo: Change produceSameValue() to take MachineRegisterInfo as an optional argument. When in SSA form, targets can use it to make more aggressive equality analysis. Machine LICM: 1. Eliminate isLoadFromConstantMemory, use MI.isInvariantLoad instead. 2. Fix a bug which prevent CSE of instructions which are not re-materializable. 3. Use improved form of produceSameValue. ARM: 1. Teach ARM produceSameValue to look pass some PIC labels. 2. Look for operands from different loads of different constant pool entries which have same values. 3. Re-implement PIC GA materialization using movw + movt. Combine the pair with a "add pc" or "ldr [pc]" to form pseudo instructions. This makes it possible to re-materialize the instruction, allow machine LICM to hoist the set of instructions out of the loop and make it possible to CSE them. It's a bit hacky, but it significantly improve code quality. 4. Some minor bug fixes as well. With the fixes, using movw + movt to materialize GAs significantly outperform the load from constantpool method. 186.crafty and 255.vortex improved > 20%, 254.gap and 176.gcc ~10%. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123905 91177308-0d34-0410-b5e6-96231b3b80d8
* Conditional moves are slightly more expensive than moves.Evan Cheng2010-11-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118985 91177308-0d34-0410-b5e6-96231b3b80d8
* putback r116983 and fix simple-fp-encoding.ll testsAndrew Trick2010-10-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116992 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r116983, which is breaking all the buildbots.Owen Anderson2010-10-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116987 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing scheduling itineraries for transfers between core registers and ↵Evan Cheng2010-10-21
| | | | | | VFP registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116983 91177308-0d34-0410-b5e6-96231b3b80d8
* Model operand cycles of vldm / vstm; also fixes scheduling itineraries of ↵Evan Cheng2010-10-07
| | | | | | vldr / vstr, etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115898 91177308-0d34-0410-b5e6-96231b3b80d8
* - Add TargetInstrInfo::getOperandLatency() to compute operand latencies. ThisEvan Cheng2010-10-06
| | | | | | | | | | | | | | allow target to correctly compute latency for cases where static scheduling itineraries isn't sufficient. e.g. variable_ops instructions such as ARM::ldm. This also allows target without scheduling itineraries to compute operand latencies. e.g. X86 can return (approximated) latencies for high latency instructions such as division. - Compute operand latencies for those defined by load multiple instructions, e.g. ldm and those used by store multiple instructions, e.g. stm. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115755 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM instruction itinerary fixes:Evan Cheng2010-09-30
| | | | | | | | | 1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones. 2. Cortex-a9 is out-of-order so model all read cycles as cycle 1. 3. Lots of other random fixes for A8 and A9. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115121 91177308-0d34-0410-b5e6-96231b3b80d8
* Separate itinerary classes for mvn from mov; for tst / teq from cmp / cmn.Evan Cheng2010-09-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115010 91177308-0d34-0410-b5e6-96231b3b80d8
* Assign bitwise binary instructions different itinerary classes from ALU ↵Evan Cheng2010-09-29
| | | | | | instructions such as add / sub. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115008 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support to model pipeline bypass / forwarding.Evan Cheng2010-09-28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115005 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove a unused instruction itinerary class.Evan Cheng2010-09-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114782 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix zero and sign extension instructions scheduling itineraries.Evan Cheng2010-09-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114780 91177308-0d34-0410-b5e6-96231b3b80d8
* More pseudo instruction scheduling itinerary fixes.Evan Cheng2010-09-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114768 91177308-0d34-0410-b5e6-96231b3b80d8
* For each instruction itinerary class, specify the number of micro-ops eachEvan Cheng2010-09-09
| | | | | | | | | | | instruction in the class would be decoded to. Or zero if the number of uOPs must be determined dynamically. This will be used to determine the cost-effectiveness of predicating a micro-coded instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113513 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up 80 column violations. No functional change.Jim Grosbach2010-06-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105350 91177308-0d34-0410-b5e6-96231b3b80d8
* Make processor FUs unique for given itinerary. This extends the limit of 32Anton Korobeynikov2010-04-18
| | | | | | | FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101754 91177308-0d34-0410-b5e6-96231b3b80d8
* Add ARMv6 itineraries.David Goodwin2009-11-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89218 91177308-0d34-0410-b5e6-96231b3b80d8
* Checkpoint NEON scheduling itineraries.David Goodwin2009-09-23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82657 91177308-0d34-0410-b5e6-96231b3b80d8
* Add Cortex-A8 VFP model.David Goodwin2009-09-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82483 91177308-0d34-0410-b5e6-96231b3b80d8
* Update Cortex-A8 instruction itineraries for integer instructions.David Goodwin2009-08-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79436 91177308-0d34-0410-b5e6-96231b3b80d8
* Turn on if-conversion for thumb2.Evan Cheng2009-08-15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79084 91177308-0d34-0410-b5e6-96231b3b80d8
* Finalize itineraries for cortex-a8 integer multiplyDavid Goodwin2009-08-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78908 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow a zero cycle stage to reserve/require a FU without advancing the cycle ↵David Goodwin2009-08-11
| | | | | | counter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78736 91177308-0d34-0410-b5e6-96231b3b80d8
* Checkpoint scheduling itinerary changes.David Goodwin2009-08-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78564 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix comment.Evan Cheng2009-07-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76693 91177308-0d34-0410-b5e6-96231b3b80d8
* Latency information for ARM v6. It's rough and not yet hooked up. Right now ↵Evan Cheng2009-06-19
we are only using branch latency to determine if-conversion limits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73747 91177308-0d34-0410-b5e6-96231b3b80d8
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